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Injection Locked Clocking and Transmitter Equalization Techniques for Chip to Chip Interconnects
2015 · California Institute of Technology · doctoral · Electrical Engineering
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@misc{academicancestry_caltechthesis_caltechthesis_8719,
author = {{Academic Ancestry}},
title = {{Injection Locked Clocking and Transmitter Equalization Techniques for Chip to Chip Interconnects: record of a thesis}},
year = {2026},
url = {https://academicancestry.org/thesis/caltechthesis/caltechthesis%3A8719},
note = {read on 2026-10-22}
}apa
Academic Ancestry. (2026, October 22). Injection Locked Clocking and Transmitter Equalization Techniques for Chip to Chip Interconnects: Record of a thesis [Read on 2026-10-22]. https://academicancestry.org/thesis/caltechthesis/caltechthesis%3A8719